1. Field of the Invention
The present invention relates to computer systems using at least one bus bridge to interface with at least one central processing unit, a video graphics processor, random access memory and input-output peripheral devices together, and more particularly, in utilizing at least one bus bridge in a computer system to enable the computer system to interface with more than one input-output device of the same type.
2. Description of the Related Technology
Use of computers, especially personal computers, in business and at home is becoming more and more pervasive because the computer has become an integral tool of most information workers who work in the fields of accounting, law, engineering, insurance, services, sales and the like. Rapid technological improvements in the field of computers have opened many new applications heretofore unavailable or too expensive for the use of older technology mainframe computers. These personal computers may be used as stand-alone workstations (high end individual personal computers) or linked together in a network by a xe2x80x9cnetwork serverxe2x80x9d which is also a personal computer which may have a few additional features specific to its purpose in the network. The network server may be used to store massive amounts of data, and may facilitate interaction of the individual workstations connected to the network for electronic mail (xe2x80x9cE-mailxe2x80x9d), document databases, video teleconferencing, white boarding, integrated enterprise calendar, virtual engineering design and the like. Multiple network servers may also be interconnected by local area networks (xe2x80x9cLANxe2x80x9d) and wide area networks (xe2x80x9cWANxe2x80x9d).
A significant part of the ever-increasing popularity of the personal computer, besides its low cost relative to just a few years ago, is its ability to run sophisticated programs and perform many useful and new tasks. Personal computers today may be easily upgraded with new peripheral devices for added flexibility and enhanced performance. A major advance in the performance of personal computers (both workstation and network servers) has been the implementation of sophisticated peripheral devices such as video graphics adapters, local area network interfaces, SCSI bus adapters, full motion video, redundant error checking and correcting disk arrays, and the like. These sophisticated peripheral devices are capable of data transfer rates approaching the native speed of the computer system microprocessor central processing unit (xe2x80x9cCPUxe2x80x9d). The peripheral devices"" data transfer speeds are achieved by connecting the peripheral devices to the microprocessor(s) and associated system random access memory through high-speed expansion local buses. Most, notably, a high speed expansion local bus standard has emerged that is microprocessor independent and has been embraced by a significant number of peripheral hardware manufacturers and software programmers. This high-speed expansion bus standard is called the xe2x80x9cPeripheral Component Interconnectxe2x80x9d or xe2x80x9cPCI.xe2x80x9d A more complete definition of the PCI local bus may be found in the PCI Local Bus Specification, revision 2.1; PCI/PCI Bridge Specification, revision 1.0; PCI System Design Guide, revision 1.0; PCI BIOS Specification, revision 2.1, and Engineering Change Notice (xe2x80x9cECNxe2x80x9d) entitled xe2x80x9cAddition of xe2x80x98New Capabilitiesxe2x80x99 Structure,xe2x80x9d dated May 20, 1996, the disclosures of which are hereby incorporated by reference. These PCI specifications and ECN are available from the PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214.
A computer system has a plurality of information (data and address) buses such as a host bus, a memory bus, at least one high speed expansion local bus such as the,PCI bus, and other peripheral buses such as the Small Computer System Interface (SCSI), Extension to Industry Standard Architecture (EISA), and Industry Standard Architecture (ISA). The microprocessor(s) of the computer system communicates with main memory and with the peripherals that make up the computer system over these various buses. The microprocessor(s) communicates to the main memory over a host bus to memory bus bridge. The peripherals, depending on their data transfer speed requirements, are connected to the various buses which are connected to the microprocessor host bus through bus bridges that detect required actions, arbitrate, and translate both data and addresses between the various buses.
Increasingly sophisticated microprocessors have revolutionized the role of the personal computer by enabling complex applications software to run at mainframe computer speeds. The latest microprocessors have brought the level of technical sophistication to personal computers that, just a few years ago, was available only in mainframe and mini-computer systems. Some representative examples of these new microprocessors are the xe2x80x9cPENTIUMxe2x80x9d and xe2x80x9cPENTIUM PROxe2x80x9d (registered trademarks of Intel Corporation). Advanced microprocessors are also manufactured by Advanced Micro Devices, Cyrix, IBM and Motorola.
These sophisticated microprocessors have, in turn, made possible running complex application programs using advanced three dimensional (xe2x80x9c3-Dxe2x80x9d) graphics for computer aided drafting and manufacturing, engineering simulations, games and the like. Increasingly complex 3-D graphics require higher speed access to ever-larger amounts of graphics data stored in memory. This memory may be part of the video graphics processor system, but, preferably, would be best (lowest cost) if part of the main computer system memory. Intel Corporation has proposed a low cost but improved 3-D graphics standard called the xe2x80x9cAccelerated Graphics Portxe2x80x9d (AGP) initiative. With AGP 3-D, graphics data, in particular textures, may be shifted out of the graphics controller local memory to computer system memory. The computer system memory is lower in cost than the graphics controller local memory and is more easily adapted for a multitude of other uses besides storing graphics data.
The proposed Intel AGP 3-D graphics standard defines a high-speed data pipeline, or xe2x80x9cAGP bus,xe2x80x9d between the graphics controller and system memory. This AGP bus has sufficient bandwidth for the graphics controller to retrieve textures from system memory without materially affecting computer system performance for other non-graphics operations. The Intel 3-D graphics standard is a specification that provides signal, protocol, electrical, and mechanical specifications for the AGP bus and devices attached thereto. This specification is entitled xe2x80x9cAccelerated Graphics Port Interface Specification version 2.0,xe2x80x9d dated May 4, 1998; and also xe2x80x9cAccelerated Graphics Port Interface Specification version 1.0,xe2x80x9d dated Jul. 31, 1996 are hereby incorporated by reference. The AGP specification, both versions 2.0 and 1.0, are available from Intel Corporation, Santa Clara, Calif.
The AGP interface specification uses the 66 MHz PCI (Revision 2.1) specification as an operational baseline, with three performance enhancements to the PCI specification which are used to optimize the AGP specification for high performance 3-D graphics applications. These enhancements are: 1) pipelined memory read and write operations, 2) de-multiplexing of address and data on the AGP bus by use of side-band signals, and 3) data transfer rates of 133 MHz for data throughput in excess of 500 megabytes per second (xe2x80x9cMB/sxe2x80x9d). The remaining AGP specification does not modify the PCI specification, but rather provides a range of graphics-oriented performance enhancements for use by 3-D graphics hardware and software designers. The AGP specification is neither meant to replace or diminish full use of the PCI standard in the computer system. The AGP specification creates an independent and additional high speed local bus for use by 3-D graphics devices such as a graphics controller, wherein the other input-output (xe2x80x9cI/Oxe2x80x9d) devices of the computer system may remain on any combination of the PCI, SCSI, EISA and ISA buses.
To functionally enable this AGP 3-D graphics bus, new computer system hardware and software are required. This requires new computer system core logic designed to function as a host bus/memory bus/PCI bus to AGP bus bridge meeting the AGP specification, and new Read Only Memory Basic Input Output System (xe2x80x9cROM BIOSxe2x80x9d) and Application Programming Interface (xe2x80x9cAPIxe2x80x9d) software to make the AGP dependent hardware functional in the computer system. The computer system core logic must still meet the PCI standards referenced above and facilitate interfacing the PCI bus(es) to the remainder of the computer system. In addition, new AGP compatible device cards must be designed to properly interface, mechanically and electrically, with the AGP bus connector. A suitable computer system employing the AGP specification is shown in FIG. 1. The prior art computer system has at least one central processing unit 102 connected to a host bus 103 which, in turn, is connected to a core logic 104. The core logic 104 is a chipset of components for linking the system random access memory 106 via the memory bus 105 to the host bus 103 and the primary PCI bus 109 through DRAM control 202. The core logic 104 also contains the circuitry related to the AGP bus 107, such as AGP to memory bridge 204 and the PCI to memory bridge 212. An AGP-compliant device, such as the video graphics controller 110, is connected to the AGP bus 107. In this example, a video display 112 is connected to the video graphics controller 110. Various other I/O devices 101 are connected to the primary PCI bus 109.
Both AGP bus transactions and PCI bus transactions may be run over the AGP interface. An AGP master (graphics) device may transfer data to system memory using either AGP transactions or PCI transactions. The core logic 104 can access the AGP master device only with PCI transactions. Traffic on the AGP interface may consist of a mixture of interleaved AGP and PCI transactions. The access request and data queue structures are illustrated in FIG. 2.
AGP transactions are run in a split transaction fashion where the request for data transfer is xe2x80x9cdisconnectedxe2x80x9d from the data transfer itself. The AGP master initiates an AGP transaction with an access request. The core logic 104 responds to the access request by directing the corresponding data transfer at a later time. The fact that the access requests are separated from the data transfers allows the AGP master to issue several access requests in a pipelined fashion while waiting for the data transfers to occur. Pipelining access requests results in having several read and/or write requests outstanding in the core logic""s request queue 208 (within the AGP to memory bridge 204) at any point in time. The request queue 208 is divided into high priority and low priority sub-queues (not shown), each of which deal with respective accesses according to separate priority and ordering rules. The AGP master tracks the state of the request queue in order to limit the number of outstanding requests and identify data transactions.
The core logic 104 processes the access requests present in its request queue 208. Read data will be obtained from system memory 106 and returned at the core logic""s initiative via the read data return queue 206. Write data will be provided by the AGP device at the core logic""s direction when space is available in the core logic""s write data queue 210. Therefore, AGP transaction traffic will generally consist of interleaved access requests and data transfers.
All PCI transactions on the AGP have their own queuesxe2x80x94separate from the AGP transaction queues. Each queue has its own access and ordering rules. Not shown in FIG. 2 is the core logic queue which handles processor accesses directly to the PCI target interface 238 of the AGP master, all of which are executed as non-pipelined PCI bus transactions.
On the other end of the AGP bus 107, the AGP-compliant device (e.g., video graphics controller 110 in FIG. 1) has an AGP interface 230 with read data return queue 232, read/write request queue 234, and write data queue 236 that correspond to the read data return queue 206, read and write request queue 208, and write data queue 210 of the AGP to memory bridge 204 within the core logic 104. The AGP-compliant device also has a PCI target interface 238. The queues within the AGP interface 230 and the PCI target interface 238 are connected to the data source/sink 239 of the device.
AGP and PCI device cards are not physically or electrically interchangeable even though there is some commonality of signal functions between the AGP and PCI interface specifications. The present AGP specification only makes allowance for a single AGP device on an AGP bus. Whereas the PCI specification allows two PCI devices on a PCI bus running at 66 MHz. The single AGP device is capable of functioning in both a 1xc3x97mode (264 MB/s peak) and a 2xc3x97mode (532 MB/s peak). The AGP bus is defined as a 32-bit bus, or four bytes per data transfer. The PCI bus is defined as either a 32 bit or 64 bit bus, or four or eight bytes per data transfer, respectively. The AGP bus, however, has additional side-band signals which enables it to transfer blocks of data more efficiently than is possible using a PCI bus.
An AGP bus running in the 2xc3x97mode provides sufficient video data throughput (532 MB/s peak) to allow increasingly complex 3-D graphics applications to run on personal computers. Some personal computer uses do not require high end 3-D graphics, but would greatly benefit from having an additional AGP card slot for accepting an additional input-output device such as another video graphics card (dual head monitors), a high speed network interface card (xe2x80x9cNICxe2x80x9d), a SCSI adapter, a wide area network digital router, and the like. Since the AGP specification is comprised of a superset of the 66 MHz, 32 bit PCI specification, a PCI device may also function on the AGP bus (different card slot connectors for the AGP and PCI device cards would be necessary). Thus, embedded (directly connected to the computer system motherboard) or card slot pluggable AGP and PCI devices could share the same AGP/PCI bus, controller and arbiter of a core logic chipset used in a computer system.
What is needed is a computer system that can accommodate more than one AGP-compatible device and that has increased bandwidth to accommodate the increased number of AGP-compatible devices.
The present invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by providing in a computer system an AGP to AGP bridge that is capable of linking one or more AGP-compatible devices to a standard AGP bus that is connected to a standard AGP-compatible core logic chipset. Specifically, the present invention provides a computer system having at least one central processing unit, system memory, and a core logic capable of accepting an AGP bus. An AGP to AGP bridge is also provided that is connected to the standard AGP bus of the core logic. The AGP to AGP bridge can accommodate two or more AGP-compatible devices that can be accessed through the standard AGP bus via the AGP to AGP bridge. A PCI to memory bridge is also provided within the core logic that is connected to the AGP bus so that PCI devices may be connected to the AGP to AGP bridge and communicate with the core logic. The AGP to AGP bridge is fitted with an overall flow control logic that controls the transfer of data to or from the various AGP devices and the standard AGP bus that is connected to the core logic of the computer system.
In the preferred embodiment of the present invention, the AGP to AGP bridge has a second AGP bus and a third AGP bus. If more than two buses are present on the AGP to AGP bridge, then the control of the internal, multiple FIFOs is managed by having a data flow pointer that keeps track of how many bytes of the returning read data belong to which AGP device. The AGP to AGP bridge of the present invention can utilize a standard 32-bit AGP bus. Furthermore, the AGP to AGP bridge can be constructed as a 64-bit bus that is bifurcated into two (dual) 32-bit buses in order to enhance bandwidth. The latter embodiment allows the dual primary AGP buses to work directly with the standard (32-bit) AGP chipset. To the core logic chipset, each AGP bus behaves fully as a standard AGP device but can operate concurrently. This allows each AGP device to have its own private bus and to run at maximum speed concurrently. Another advantage of this alternate embodiment is that it can support any number of AGP devices/slots on the secondary AGP buses.
In yet another alternate embodiment of the present invention, the dual 32-bit buses can be combined to form a single 64-bit bus to increase the available bandwidth. In this alternate embodiment, the AGP to AGP bridge can be an external application specific integrated circuit (ASIC) that interfaces directly with the standard AGP core logic chipset. To the core logic chipset, the AGP to AGP bridge behaves fully as a superset of the standard 32-bit AGP device. This allows doubling of the bus bandwidth without running the bus at higher clock frequencies, i.e. 2xc3x9766 MHz. Currently, most AGP devices could not meet the AC timing at 66 MHz. Therefore, this alternate embodiment is the only viable solution for doubling the bus bandwidth without running the bus at 133 MHz. In yet another alternate embodiment, the AGP to AGP bridge can accommodate the single 64-bit AGP bus (connected to a special 64-bit core logic chipset) for increased performance.
In yet another alternate embodiment of the present invention, the AGP to AGP bridge acts as a bus repeater and allows the AGP to AGP bridge to work with standard xe2x80x9coff-the-shelfxe2x80x9d bi-directional transceivers or FIFOs. The alternate embodiment enables the AGP bus to be extended, thus allowing the computer system to support more than one AGP device/slot. However, this alternate embodiment adds additional latency to all the bus transactions and requires the core logic chipset to control the data flow from both directions.